EP910ILC-25 vs EP910IPC-50 Comparaison
Comparaison détaillée côte à côte de EP910ILC-25 par Intel et EP910IPC-50 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910ILC-25 | EP910IPC-50 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $13,85 |
| Family | EP910 Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| User I/O Pins | 36 | 24 |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM cell |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Boîtier | 44-pin JLCC (windowed ceramic) | 40-pin Ceramic DIP (IPC, windowed) |
| Type de montage | Surface Mount | Through-Hole (DIP) |
| Température de fonctionnement | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Tension d'alimentation | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Statut RoHS | non_compliant (ceramic windowed package) | [DATA_NEEDED: not stated in verified data] |
| Statut du cycle de vie | Obsolete - last time buy was late 1990s | — |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |