EP910LC-25 vs EP910LC44 Comparaison
Comparaison détaillée côte à côte de EP910LC-25 par Intel et EP910LC44 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP910LC-25 | EP910LC44 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2,20 | $8,95 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 16 | 12 |
| Boîtier | 28-pin PLCC (LC suffix) | 44-pin PLCC (J-leaded) |
| Type de montage | Surface Mount | — |
| Technology | CMOS (EPROM-based) | — |
| Operating Voltage | [DATA_NEEDED: VCC range] | — |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Programmable | Yes (EPROM, UV-erasable on windowed variants) | — |
| I/O Pins | [DATA_NEEDED: I/O count] | 24 |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Product Family | — | Classic EPLD (EP910 Series) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Global Clock Inputs | — | 2 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| Programming Method | — | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |
| Logic Compatibility | — | TTL-compatible CMOS I/O |