EP910LC-35H vs EP910DC-30 Comparaison
Comparaison détaillée côte à côte de EP910LC-35H par Altera et EP910DC-30 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910LC-35H | EP910DC-30 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $25,00 | $15,60 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910 series) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | 40-pin Ceramic DIP (H suffix) | DIP-40 (through-hole, 600 mil) |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | 36 |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | UV-Erasable / OTP |
| Logic Levels | TTL compatible | — |
| Courant de repos | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| Type de montage | Through-hole (Ceramic DIP) | Through-Hole |
| Statut RoHS | unknown | — |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Tension d'alimentation | — | 5 V |
| Process Technology | — | CMOS |