EP910LC-40H vs EP910LC-35 Comparaison
Comparaison détaillée côte à côte de EP910LC-40H par Altera et EP910LC-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910LC-40H | EP910LC-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $18,75 |
| Family | Classic EPLD (EP910) | Classic (EP910) |
| Macro Cells | 24 | — |
| Usable Gates | 450 | 450 |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | — |
| Propagation Delay (tPD) | 40 ns max | 35 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Boîtier | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | PLCC-44 (J-lead, LC suffix) |
| Type de montage | Through-Hole (THT) | — |
| Température de fonctionnement | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | 0C to +70C (commercial) |
| Speed Grade | -40 (40 ns tPD) | — |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | — |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | — |
| Statut RoHS | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | Not applicable (legacy product) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Nombre de broches | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |