EP910LC44-40 vs EP910LC44 Comparaison
Comparaison détaillée côte à côte de EP910LC44-40 par Altera et EP910LC44 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP910LC44-40 | EP910LC44 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $8,95 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Product Terms (Total) | 240 | — |
| I/O Pins | 24 (bidirectional) | 24 |
| Dedicated Inputs | 12 | 12 |
| Total Inputs | 36 | — |
| Global Clock Inputs | 2 | 2 |
| Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Compatibility | TTL-compatible I/O | TTL-compatible CMOS I/O |
| Boîtier | 44-pin PLCC (Plastic Leaded Chip Carrier) | 44-pin PLCC (J-leaded) |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Programming Method | JEDEC file via LP6/MP9 or compatible programmer | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| Type de montage | Surface Mount | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified data] |
| Product Family | — | Classic EPLD (EP910 Series) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |