EP910LC44 vs EP910LC-30 Comparaison
Comparaison détaillée côte à côte de EP910LC44 par Altera et EP910LC-30 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EP910LC44 | EP910LC-30 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,95 | $22,50 |
| Product Family | Classic EPLD (EP910 Series) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 | — |
| Total Product Terms | 240 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Total Input Pins | 36 (12 dedicated + 24 I/O as inputs) | — |
| Global Clock Inputs | 2 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (nominal, TTL) |
| Propagation Delay (LC grade) | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] | — |
| Propagation Delay (LC-30 grade) | 33 ns (per EP910LC44-30 verified data) | — |
| Process Technology | CMOS | CMOS (EPROM-based) |
| Boîtier | 44-pin PLCC (J-leaded) | — |
| Température de fonctionnement | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] | — |
| Programming Method | EPROM (erasable UV for ceramic; OTP for plastic PLCC) | — |
| Architecture | AND-OR sum-of-products with programmable macrocell feedback | — |
| Logic Compatibility | TTL-compatible CMOS I/O | — |
| Statut RoHS | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS status] |
| Macrocell Count | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Maximum Toggle Frequency | — | 62 MHz |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |