EP910LI-35T vs EP910LI-40 Comparaison
Comparaison détaillée côte à côte de EP910LI-35T par Intel et EP910LI-40 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910LI-35T | EP910LI-40 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,50 | $12,90 |
| Family | Classic EPLD (EP910) | — |
| Logic Elements | 24 macrocells | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 40 ns |
| Maximum Toggle Frequency (fMAX) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, EPROM-based | Low-power CMOS (L-suffix) |
| Boîtier | 44-pin PLCC (JEDEC) | PLCC-44 (J-lead, windowed ceramic) |
| Température de fonctionnement | -40C to +85C (industrial, 'I' suffix) | -40C to +85C (industrial, I-suffix) |
| Type de montage | Surface Mount / Socket | Surface Mount (socket-compatible) |
| Programming Method | EPROM (UV-erasable for windowed versions) | — |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Number of I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (windowed ceramic PLCC, legacy) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 bidirectional |
| Maximum Logic Inputs | — | 36 |
| Product Terms | — | 240 |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |