EP910LI44 vs EP910LI-50 Comparaison
Comparaison détaillée côte à côte de EP910LI44 par Altera et EP910LI-50 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910LI44 | EP910LI-50 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,20 | $65,00 |
| Family | Classic EPLD | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, One-Time-Programmable | — |
| Macrocells | 24 | 24 |
| Package Type | PLCC-44 (J-lead, surface mount) | CERDIP-40 (L) |
| Total Pins | 44 | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O | 24 | — |
| Maximum Logic Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Flip-Flops | 24 | — |
| External Clocks | 2 | — |
| Maximum Propagation Delay | [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) | 5 V +/- 10% |
| Operating Temperature (L grade) | -40 °C to +85 °C (industrial) | — |
| Technology | CMOS | CMOS, UV-erasable EPROM |
| Programmability | UV-erasable (windowed) or OTP | — |
| Statut RoHS | non-compliant (original PLCC-44 lead finish) | [DATA_NEEDED: RoHS status] |
| Type de montage | Surface Mount (PLCC socket compatible) | — |
| Programming Method | Altera Logic Programmer card / Data I/O / third-party EPROM programmers | EPROM programmer (UV-erasable window) |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 50 ns |
| Package Pin Count | — | 40 |
| Température de fonctionnement | — | -40C to +85C (industrial) |
| Logic Blocks | — | Classic AND/OR array architecture |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |