EP910PC-20 vs EP910PC30T Comparaison
Comparaison détaillée côte à côte de EP910PC-20 par Altera et EP910PC30T par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PC-20 | EP910PC30T |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,40 | $8,85 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Usable Gates | 900 | — |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Boîtier | PDIP-24 (PC suffix) | 24-pin PDIP (PC) |
| Nombre de broches | 24 | 24 |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Method | EPROM programmer, JEDEC fuse map | — |
| Type de montage | Through-Hole (DIP) | Through-Hole (THT) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Speed Grade | — | -30 (30 ns tPD) |
| Programming Technology | — | EPROM (OTP in plastic package, UV-erasable in windowed package) |