EP910PI-20 vs EP910JC-30 Comparaison
Comparaison détaillée côte à côte de EP910PI-20 par Altera et EP910JC-30 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PI-20 | EP910JC-30 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $9,75 |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | — |
| Boîtier | PDIP-40 (PI suffix) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Type de montage | Through-Hole | Surface Mount (socket-mountable) |
| Supply Voltage (VCC) | 5 V (+/- 5%) | — |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS EPROM, UV-erasable |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Family | — | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |