EP910PI-20 vs EP910PI-25 Comparaison
Comparaison détaillée côte à côte de EP910PI-20 par Altera et EP910PI-25 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PI-20 | EP910PI-25 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $10,95 |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | — |
| Boîtier | PDIP-40 (PI suffix) | PDIP-40 (Plastic DIP) |
| Type de montage | Through-Hole | Through-Hole |
| Supply Voltage (VCC) | 5 V (+/- 5%) | 5 V nominal |
| Température de fonctionnement | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | — |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| Statut RoHS | unknown | Non-compliant (PDIP package) |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| I/O Pins | — | 24 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Process Technology | — | 5 V CMOS (EPROM-based) |
| Nombre de broches | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |