EPC1441PI8 vs EPC1441LI20 Comparaison
Comparaison détaillée côte à côte de EPC1441PI8 par Intel et EPC1441LI20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1441PI8 | EPC1441LI20 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,25 | $8,10 |
| Type de mémoire | OTP Configuration PROM | OTP Configuration PROM (PROM) |
| Taille de mémoire | 440 kb (440,800 bits) | — |
| Configuration Interface | Serial, 4-pin (nSTATUS, nCONFIG, DCLK, DATA0) | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Tension d'alimentation | 5.0 V | 3.3 V |
| Programmability | One-Time Programmable (OTP) | — |
| Boîtier | 8-PDIP (8-pin Plastic DIP) | 20-pin PLCC (J-lead, 9x9 mm) |
| Type de montage | Through-Hole | — |
| Supported FPGA Families | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Cascading Support | Yes (nCASC output for multi-device chains) | — |
| Programming Voltage | Not required (single 5.0 V supply) | — |
| Température de fonctionnement | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| Lead-Free / RoHS | Not RoHS compliant (PDIP, SnPb finish) | — |
| Niveau MSL | 1 (unlimited) | [DATA_NEEDED: MSL rating] |
| Supported Configuration Modes | Passive serial (PS) only | — |
| Manufacturer | Intel (formerly Altera) | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Pin Pitch | — | 1.27 mm |
| Programming Method | — | One-Time-Programmable via Altera programming hardware |
| Statut RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |