EPC144LC20 vs EPC1L20 Comparaison
Comparaison détaillée côte à côte de EPC144LC20 par Intel et EPC1L20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC144LC20 | EPC1L20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Dernier achat | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,10 | $3,75 |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Type d'interface | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | — |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | — |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Boîtier | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-pin PLCC (9x9 mm) |
| Nombre de broches | 20 | — |
| Type de montage | Surface Mount | Through-Hole / Socket |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| Niveau MSL | 3 (168 hours) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status per Intel PCN] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| Sans halogène | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Type de mémoire | — | OTP Configuration PROM (Flash) |
| Taille de mémoire | — | 1 Mbit |
| Configuration Clock (max) | — | 8 MHz |
| Flash Access Time | — | 90 ns (approx.) |
| Max Read Bandwidth | — | 160 Mbps (16-bit DQ bus) |
| Interface | — | Serial / FPP configuration + JTAG (IEEE 1149.1) |
| Tension d'alimentation | — | 3.3 V (typical) |
| Programmability | — | One-Time Programmable (OTP) |
| JTAG / ISP Support | — | Yes (IEEE 1149.1) |
| Compatible FPGA Series | — | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families |