EPC144LC20 vs EPC2L1696-10F Comparaison
Comparaison détaillée côte à côte de EPC144LC20 par Intel et EPC2L1696-10F par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC144LC20 | EPC2L1696-10F |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,10 | $0,00 |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Type d'interface | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | — |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | 3.3 V |
| Température de fonctionnement | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Boîtier | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-pin PLCC |
| Nombre de broches | 20 | — |
| Type de montage | Surface Mount | Surface Mount |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| Niveau MSL | 3 (168 hours) | [DATA_NEEDED: MSL level] |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status per Intel PCN] | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Sans halogène | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Device Type | — | Configuration EPROM for SRAM-based LUT FPGAs |
| Supported Logic Density | — | 1696 LUTs |
| Configuration Interface | — | 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF) |
| Memory Technology | — | CMOS EEPROM |
| Access Time | — | 10 ns (speed grade -10) |
| Maximum DCLK Frequency | — | [DATA_NEEDED: DCLK max frequency] |
| Program / Erase Cycles | — | >= 100,000 cycles |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| In-System Programming | — | Yes (4-wire JTAG-style interface) |