EPC16QI100N vs EPC16QI100TBAC Comparaison
Comparaison détaillée côte à côte de EPC16QI100N par Altera et EPC16QI100TBAC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPC16QI100N | EPC16QI100TBAC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,40 | $15,95 |
| Taille de mémoire | 16 Mb | — |
| Type de mémoire | Flash (in-system programmable) | Flash (Enhanced Configuration Device) |
| Programmable Type | In System Programmable | — |
| Configuration Interface | Serial | — |
| Maximum Configuration Clock | 33 MHz | 40 MHz |
| Supply Voltage - Operating | 3.0 V to 3.6 V | — |
| Température de fonctionnement | -40C to +85C | -40C to +85C (industrial) |
| Boîtier / Format | 100-PQFP (20 x 14 mm) | — |
| Type de montage | Surface Mount | Surface Mount (PQFP) |
| Number of Terminals | 100 | — |
| Package Style | Flatpack / PQFP | — |
| Family Name | EPC16 | — |
| Application | FPGA configuration memory | — |
| Statut RoHS | Compliant | — |
| Reprogrammability | Yes, in-system (IEEE 1532) | — |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Tension d'alimentation | — | 3.3 V |
| Configuration Modes | — | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) |
| Number of Configuration Pages | — | Up to 8 (selectable via PGM[2..0]) |
| Boîtier | — | 100-pin PQFP (20 x 14 mm) |
| In-System Programmable | — | Yes (via JTAG / IEEE 1149.1) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan and programming) |
| Supported FPGA Families | — | Altera Stratix, Cyclone, Arria series |
| Data Compression | — | Supported (15-30% density gain depending on target FPGA) |
| Niveau MSL | — | 3 (168 hours) |
| Lead-Free / RoHS | — | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] |
| Dynamic Reconfiguration | — | Yes (page mode via PGM[2..0] pins) |
| Configuration Controller | — | Integrated |
| Programming Interface | — | JTAG / 4-wire passive serial |