EPC16U88 vs EPC16UC88 Comparaison
Comparaison détaillée côte à côte de EPC16U88 par Altera et EPC16UC88 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16U88 | EPC16UC88 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Obsolete | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,85 | $0,00 |
| Memory Density | 16 Mb | — |
| Device Family | EPC16 (Enhanced Configuration Device) | — |
| Fonction | Configuration PROM for SRAM-based LUT FPGAs | — |
| Boîtier | 88-ball UBGA (UltraBGA), 11x8 mm | 88-UBGA (11x8) |
| Package Suffix Code | U88 (UBGA-88) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| I/O Voltage Tolerance | 5 V tolerant I/O | — |
| Configuration Modes Supported | FPP, PS, AS (with target FPGA) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Multi-Device Cascading | Yes (page-mode support) | — |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature] |
| Compatible FPGA Families | Altera Stratix, Cyclone, Arria series | — |
| Configuration Interface Width | Up to 8-bit parallel (FPP) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tension d'alimentation | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Type de montage | — | Surface mount |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |