EPC16UC88AA vs EPC16UC88 Comparaison
Comparaison détaillée côte à côte de EPC16UC88AA par Altera et EPC16UC88 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16UC88AA | EPC16UC88 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $20,45 | $0,00 |
| Programmable Type | In System Programmable | — |
| Taille de mémoire | 16Mb (16,777,216 bits) | — |
| Type de mémoire | EEPROM / Flash-based non-volatile | — |
| On-Chip Decompression | Yes (~35% bitstream compression) | — |
| Boîtier / Format | 88-UBGA (11x8 mm) | — |
| Packaging | Tray | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Interface | Serial + JTAG ISP | — |
| Configuration Interface | DCLK / DATA / nCONFIG / nSTATUS handshake to target FPGA | — |
| Cascade Support | Up to 8 devices in series | — |
| Température de fonctionnement | 0 C to 70 C | [DATA_NEEDED: operating temperature] |
| Lead Free | Yes (per DigiKey listing) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Target FPGAs | Altera FLEX 10K, APEX 20K, ACEX 1K and compatible families | — |
| Type de montage | Surface Mount | Surface mount |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tension d'alimentation | — | 3.3 V core and I/O |
| Boîtier | — | 88-UBGA (11x8) |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |