EPC16UC88N vs EPC16UC88 Comparaison
Comparaison détaillée côte à côte de EPC16UC88N par Altera et EPC16UC88 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16UC88N | EPC16UC88 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | NRND | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $0,00 |
| Taille de mémoire | 16 Mbit (16,777,216 bits) | — |
| Programmable Type | In System Programmable | — |
| Supply Voltage (Vcc) | 3.0 V to 3.6 V | — |
| Configuration Modes | Passive Serial (PS), Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), JTAG | — |
| On-Chip Decompression | Yes (Altera proprietary) | — |
| Boîtier / Format | 88-UBGA (11x8 mm) / 88-LFBGA | — |
| Nombre de broches | 88 | — |
| Température de fonctionnement | 0 °C to +70 °C | [DATA_NEEDED: operating temperature] |
| Bus-Hold on Data Lines | Yes | — |
| Standby Mode | Yes (reduced power consumption) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | Supported |
| Programming Interface | JTAG (in-system) / Serial (in-system) | — |
| On-Chip Oscillator | Yes (internal configuration clock) | — |
| Lead-Free / RoHS | Lead-Free (per datasheet) | — |
| Type de montage | Surface Mount | Surface mount |
| Packaging | Tray | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tension d'alimentation | — | 3.3 V core and I/O |
| Boîtier | — | 88-UBGA (11x8) |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |