EPC16UC88N vs EPC16UC88II Comparaison
Comparaison détaillée côte à côte de EPC16UC88N par Altera et EPC16UC88II par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16UC88N | EPC16UC88II |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $10,85 |
| Taille de mémoire | 16 Mbit (16,777,216 bits) | — |
| Programmable Type | In System Programmable | — |
| Supply Voltage (Vcc) | 3.0 V to 3.6 V | — |
| Configuration Modes | Passive Serial (PS), Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), JTAG | — |
| On-Chip Decompression | Yes (Altera proprietary) | — |
| Boîtier / Format | 88-UBGA (11x8 mm) / 88-LFBGA | — |
| Nombre de broches | 88 | — |
| Température de fonctionnement | 0 °C to +70 °C | -40C to +85C (industrial) |
| Bus-Hold on Data Lines | Yes | — |
| Standby Mode | Yes (reduced power consumption) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| Programming Interface | JTAG (in-system) / Serial (in-system) | — |
| On-Chip Oscillator | Yes (internal configuration clock) | — |
| Lead-Free / RoHS | Lead-Free (per datasheet) | Compliant per Intel product page |
| Type de montage | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| Type de mémoire | — | FPGA Configuration PROM (non-volatile) |
| Density | — | 16 Mb (2 Mbyte) |
| Core Supply Voltage (VCC) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V |
| Boîtier | — | 88-ball UFBGA |
| Configuration Interface | — | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| Architecture | — | CMOS serial configuration memory |
| Error Detection | — | Frame-level CRC during FPGA load |
| Daisy-Chain Support | — | Yes (multi-FPGA boards) |
| In-System Programming | — | Yes (via JTAG or AS mode) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Compatible FPGA Families | — | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur |