EPC16UC88SS vs EPC16UC88 Comparaison
Comparaison détaillée côte à côte de EPC16UC88SS par Intel et EPC16UC88 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC16UC88SS | EPC16UC88 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,45 | $0,00 |
| Manufacturer | Intel (formerly Altera) | — |
| MPN | EPC16UC88SS | — |
| Part Type | FPGA Configuration PROM | — |
| Memory Density | 16 Mbit | — |
| Interface | 4-pin serial (nCS, DCLK, DATA, ASDI) | — |
| Configuration Mode | Active Serial (AS) - compressed | — |
| Boîtier | SOIC-8 | 88-UBGA (11x8) |
| Operating Voltage | 3.3 V nominal (2.7 V to 3.6 V range) | — |
| Maximum DCLK Frequency | 100 MHz (fast mode) | — |
| Program/Erase Endurance | 100,000 cycles (per sector) | — |
| Data Retention | 20 years minimum | — |
| Température de fonctionnement | -40C to +85C (commercial) | [DATA_NEEDED: operating temperature] |
| Cascading | Multi-device chain supported via nCS-OE daisy | — |
| In-System Programming | Yes (JTAG/ASDI) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Niveau MSL | 1 (unlimited floor life at <=30C/85% RH) | — |
| Compatible FPGA Families | Cyclone II/III/IV, Stratix II/III/IV, Arria GX | — |
| Compression Support | Yes (Intel/Altera compressed bitstream) | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tension d'alimentation | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Type de montage | — | Surface mount |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |