EPC2C20 vs EPC2CC20N Comparaison
Comparaison détaillée côte à côte de EPC2C20 par Altera et EPC2CC20N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2C20 | EPC2CC20N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $10,85 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Boîtier | [DATA_NEEDED: package] | PLCC-20 |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Fonction | — | Configuration device for SRAM-based LUT FPGAs |
| Density | — | [DATA_NEEDED: bitstream density in bits] |
| Configuration Interface | — | 16-bit parallel (FPP) / Passive Serial (PS) |
| Supply Voltage (VCC) | — | 3.3 V |
| Programming Interface | — | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| Température de fonctionnement | — | [DATA_NEEDED: industrial/commercial temp range] |
| Type de montage | — | Surface Mount (PLCC-20 socket compatible) |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |