EPC2LC20CAD vs EPC2LC20 Comparaison
Comparaison détaillée côte à côte de EPC2LC20CAD par Altera et EPC2LC20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LC20CAD | EPC2LC20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $7,20 |
| Type de mémoire | Configuration PROM (Flash) | Non-volatile configuration PROM |
| Memory Capacity | 1.6 Mbit | — |
| Tension d'alimentation | 3.3 V (nominal) | — |
| I/O Voltage Tolerance | 5 V tolerant | — |
| Configuration Mode | Serial (bit-wide, Altera FPGAs) | — |
| Program Interface | IEEE Std 1149.1 JTAG (in-system programmable) | — |
| Boîtier | 20-pin J-lead PLCC (PLCC-20) | 20-pin PLCC (J-lead, 9x9 mm) |
| Nombre de broches | 20 | — |
| Température de fonctionnement | -40C to +85C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Maximum Input Voltage (DC) | -0.3 V to +7.0 V | — |
| Input Undershoot/Overshoot | -2.0 V to +7.0 V for <100 mA, <20 ns no-load | — |
| Compatible FPGA Families | APEX 20K, ACEX 1K, Cyclone, Stratix | — |
| Programming Method | JTAG ISP (no external programmer required) | — |
| Statut RoHS | Compliant | Non-Compliant (original Altera Pb-containing part) |
| Type de montage | Surface Mount / Through-hole (PLCC socket) | Surface Mount |
| Taille de mémoire | — | 1.6 Mbit |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |