EPC2LC20NUBAF48 vs EPC2LC20N Comparaison
Comparaison détaillée côte à côte de EPC2LC20NUBAF48 par Altera et EPC2LC20N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LC20NUBAF48 | EPC2LC20N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,40 | $7,40 |
| Type de mémoire | Non-volatile flash configuration PROM | Flash |
| Memory Density | 2 Mbit (2,097,152 bits) | — |
| Core Supply Voltage (VCC) | 3.3 V (low-voltage 'L' variant) | — |
| I/O Logic Levels | 3.3 V LVCMOS (5V-tolerant inputs) | — |
| Configuration Interface | Altera serial (DATA, DCLK, nCS, ASDO) | — |
| JTAG / ISP Support | IEEE 1532 / JTAG in-system programming | — |
| Cascade Support | Yes - dedicated nCASC pin for 2-device chains | — |
| Programming Voltage | Internal 3.3V generation, no external VPP | — |
| FPGA Compatibility | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 6000 | — |
| Boîtier | 20-pin Ultra FineLine BGA (UBGA, NU suffix) | 20-pin PLCC (J-Lead, 9x9 mm) |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Configuration Clock | Internal oscillator (DCLK output to FPGA) | — |
| Programming Tools | Quartus II Programmer, ByteBlaster II, USB-Blaster | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Fonction | — | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Taille de mémoire | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage VCCIO | — | 4.75 V to 5.25 V |
| Configuration Clock Frequency | — | 8 MHz (max) |
| Interface | — | Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| JTAG Support | — | IEEE 1149.1 / IEEE 1532 compliant |
| Type de montage | — | Surface Mount |
| Packaging | — | Tube |
| Supported FPGA Families | — | Altera APEX, Cyclone, Stratix, ACEX, MAX 7000 |