EPC81500RC304-3 vs EPC16UC88 Comparaison
Comparaison détaillée côte à côte de EPC81500RC304-3 par Altera et EPC16UC88 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPC81500RC304-3 - Enhanced Configuration Device for SRAM FPGAs | Altera
EPC81500RC304-3 Obsolete
Comparaison des spécifications
| Paramètre | EPC81500RC304-3 | EPC16UC88 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Obsolete | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,90 | $0,00 |
| Device Type | Enhanced Configuration Device (Flash-based FPGA configuration memory) | In-system programmable configuration PROM for FPGAs |
| Target FPGA Families | Altera FLEX 8000, FLEX 10K, ACEX 1K, APEX series SRAM-based LUT FPGAs | — |
| Configuration Memory Size | 8 Mbit | — |
| Interface Modes | Parallel-byte and serial bitstream modes | — |
| Programming Interface | JTAG (IEEE 1149.1) and byte-wide parallel | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Voltage VCCIO | 3.3 V or 5.0 V tolerant | — |
| Plage de température de fonctionnement | 0 C to +70 C (commercial) | — |
| Boîtier | 304-pin PQFP (RC304) | 88-UBGA (11x8) |
| Type de montage | Surface Mount | Surface mount |
| Nombre de broches | 304 | — |
| Configuration Clock | DCLK generated internally or externally to target FPGA | — |
| Multi-Device Support | Yes - daisy-chain configuration of multiple FPGAs | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Memory Capacity | — | 16 Mb |
| Tension d'alimentation | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |