EPF10K100EQC240-1 vs EPF10K100BQC240-1 Comparaison
Comparaison détaillée côte à côte de EPF10K100EQC240-1 par Altera et EPF10K100BQC240-1 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPF10K100BQC240-1 - 100K FLEX-10K FPGA, 240-PQFP | Intel / Altera
EPF10K100BQC240-1 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPF10K100EQC240-1 | EPF10K100BQC240-1 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,50 | $119,00 |
| Family | FLEX 10KE | FLEX-10K (EPF10K100B) |
| Series | FLEX-10KE | FLEX-10K |
| Logic Elements / Cells | 4992 | — |
| Number of LABs / CLBs | 624 | — |
| Total RAM Bits | 49152 | 24,576 (12 × 2,048 bits per EAB) |
| Typical Gate Count | 100000 | — |
| Number of User I/Os | 189 | — |
| Supply Voltage (Core) | 2.375 V to 2.625 V | — |
| I/O Voltage | 3.3 V (MultiVolt: 1.8 V / 2.5 V / 3.3 V) | — |
| Process Technology | CMOS (0.42 µm) | 0.42 µm SRAM CMOS |
| Propagation Delay | 0.4 ns to 0.6 ns | — |
| Température de fonctionnement | 0 °C to 70 °C (Commercial) | 0 °C to +70 °C (commercial) |
| Boîtier | 240-BFQFP (PQFP240, 32 x 32 mm) | 240-pin BFQFP / PQFP (BQC suffix) |
| Type de montage | Surface Mount | Surface Mount |
| Style de montage | SMD / SMT | — |
| Statut RoHS | [DATA_NEEDED: rohs] | [DATA_NEEDED: RoHS compliance] |
| Configuration Method | SRAM (serial / JTAG) | ByteBlasterMV / BitBlaster / JTAG |
| Embedded Memory | EABs (12 blocks × 2048 bits) | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| Status | Obsolete (EOL) | — |
| Logic Elements (LEs) | — | 6,144 |
| Typical Gates | — | 100,000 |
| Embedded Array Blocks (EABs) | — | 12 |
| Maximum User I/O | — | 189 |
| Supply Voltage (VCCINT / VCCIO) | — | 4.75 V to 5.25 V |
| Speed Grade | — | -1 |
| Combinatorial tPD (typical) | — | 11 ns |
| Package Dimensions | — | 32 mm × 32 mm |
| Niveau MSL | — | 3 (per JEDEC J-STD-020) |