EPF10K200SBC356-3 vs EPF10K200SBC356-2 Comparaison
Comparaison détaillée côte à côte de EPF10K200SBC356-3 par Intel et EPF10K200SBC356-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SBC356-3 | EPF10K200SBC356-2 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $87,50 | $178,00 |
| Family | FLEX 10K | FLEX 10KS (Embedded Programmable Logic) |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Typical Gates | 200,000 | — |
| Logic Elements (Cells) | 9,984 | — |
| Logic Array Blocks (LABs) | 1,248 | 1248 |
| Embedded Array Blocks (EABs) | 12 | — |
| Total EAB RAM | 98,304 bits | — |
| User I/Os | 470 (package exposes 274 bonded-out) | 274 |
| Flip-Flops | 4,992 | — |
| Process Technology | 0.22 um CMOS, 4 metal layers | 0.22 um CMOS |
| Core Supply Voltage | 2.375 V to 2.625 V | — |
| Propagation Delay | 0.4 ns | 0.4 ns (per datasheet) |
| Internal Performance (fmax) | 250 MHz | — |
| Température de fonctionnement | 0 C to 70 C (Commercial) | 0C to +70C (Commercial) |
| Boîtier | PBGA-356 (35 x 35 mm, 1.27 mm pitch) | 356-LBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Mode | Passive Serial / Passive Parallel / JTAG | — |
| MultiVolt I/O | 2.5 V / 3.3 V / 5.0 V | — |
| Logic Family | CMOS | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | Non-compliant (legacy part) |
| Series | — | FLEX 10KS |
| Logic Elements / Cells | — | 9984 |
| Embedded Memory Bits (EAB) | — | 98304 |
| System Gates | — | 200,000 |
| Number of I/O Banks | — | 8 |
| Supply Voltage (Core) | — | 2.5 V (2.375 V - 2.625 V) |
| I/O Voltage (PCI-compatible) | — | 3.3 V / 5.0 V tolerant |
| Speed Grade | — | -2 |
| Configuration | — | SRAM-based (volatile, requires configuration device) |
| Boundary Scan | — | Yes (JTAG IEEE 1149.1) |
| PLL | — | Yes (on-chip) |