EPF10K200SFC484-2 vs EPF10K200SFC484-2N Comparaison
Comparaison détaillée côte à côte de EPF10K200SFC484-2 par Altera et EPF10K200SFC484-2N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SFC484-2 | EPF10K200SFC484-2N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $88,40 | $95,00 |
| Series | FLEX 10KS | — |
| Family | FLEX 10K (FLEX-10KS subfamily) | FLEX 10KE |
| Logic Elements / Cells | 9,984 | 9,984 |
| System Gates | 200,000 | — |
| Embedded Memory (RAM bits) | 98,304 | — |
| Embedded Array Blocks (EAB) | 4 EABs x 2,048 bits | — |
| Logic Array Blocks (LAB) | 369 | — |
| User I/Os | 369 | — |
| Propagation Delay | 0.4 ns (max) | 0.4 ns |
| Nombre de broches | 484 | — |
| Package Type | FineLine BGA-484 (23 x 23 mm, 1.0 mm pitch) | — |
| Technology | 0.22 um CMOS, SRAM-based | — |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.375 V to 2.625 V (2.5 V nominal) |
| I/O Supply Voltage | 2.5 V / 3.3 V / 5 V (multiVolt I/O) | — |
| Température de fonctionnement | 0 C to +70 C (commercial) | 0°C to 70°C (Commercial) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant (lead-free) | — |
| Configuration Method | EPC configuration device, JTAG, or microcontroller | — |
| Speed Grade | -2 (faster than -3) | — |
| PLL Count | 4 | — |
| Gate Count | — | 200,000 |
| Logic Array Blocks (LABs) | — | 1,248 |
| Embedded RAM Bits | — | 98,304 (96 Kbit) |
| User I/O Pins | — | 369 |
| Number of I/Os (alt spec) | — | 470 (per digchip datasheet summary) |
| Internal Performance | — | 200 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Boîtier | — | 484-FBGA FineLine BGA, 23 x 23 mm, 1.0 mm pitch |
| Programming Interface | — | JTAG (IEEE 1149.1), SRAM configuration |
| I/O Standard Support | — | 5 V-tolerant, MultiVolt (1.8 V / 2.5 V / 3.3 V) |
| Logic Family | — | CMOS |
| Compliance / Lead Status | — | [DATA_NEEDED: RoHS status] |