EPF10K200SFC672-2 vs EPF10K200EFC672-2 Comparaison
Comparaison détaillée côte à côte de EPF10K200SFC672-2 par Altera et EPF10K200EFC672-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SFC672-2 | EPF10K200EFC672-2 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $320,00 | $210,00 |
| Series | FLEX 10KE | — |
| Logic Elements | 9,984 | 9,984 |
| System Gates | 200,000 | — |
| Logic Array Blocks (LABs) | 1,248 | 624 |
| User I/O Pins | 470 | — |
| Embedded Memory (bits) | 98,304 | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Speed Grade | -2 | -2 |
| Internal Propagation Delay | 0.4 ns | — |
| Maximum Operating Frequency | 200 MHz | — |
| Boîtier | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch | 672-BBGA (FineLine BGA) |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0 C to 70 C |
| Configuration Method | SRAM-based, passive parallel asynchronous | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| On-chip PLL | Yes | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per distributor listing) |
| Family | — | FLEX 10KE |
| Typical Gates | — | 200,000 |
| Maximum User I/Os | — | 470 |
| Embedded Memory | — | 98,304 bits |
| Embedded Array Blocks (EABs) | — | 12 |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |
| Propagation Delay | — | 0.4 ns |
| Supply Voltage (Core) | — | [DATA_NEEDED: core Vcc] |
| Programmability | — | JTAG (IEEE 1149.1) / in-system |
| Logic Family | — | CMOS |