EPF10K200SFI672-2 vs EPF10K200SFC672-1 Comparaison
Comparaison détaillée côte à côte de EPF10K200SFI672-2 par Intel et EPF10K200SFC672-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SFI672-2 | EPF10K200SFC672-1 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $99,50 | $138,75 |
| Family | FLEX 10KE | FLEX 10KE (FLEX-10KS) |
| Logic Elements | 9984 | — |
| System Gates | 200000 | — |
| Logic Array Blocks (LABs) | 1248 | — |
| User I/Os | 470 | — |
| Embedded Array Blocks (EABs) | 24 | 12 |
| Embedded Memory (EAB SRAM) | 96 Kbit | — |
| Distributed Memory | 98304 bits | — |
| Process Technology | 0.22 µm (Arrow lists 0.42 µm) | 0.22 µm CMOS, SRAM-based |
| Core Supply Voltage | 2.5 V | — |
| Boîtier | 672-pin FineLine BGA (FBGA) | — |
| Speed Grade | -2 | -1 |
| Température de fonctionnement | Industrial (-40C to +85C) | 0 °C to +70 °C (Commercial) |
| JTAG Boundary Scan | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (3.3 V, 33/66 MHz) on -1 speed grade | — |
| Programming | SRAM-based, in-system programmable | — |
| Statut RoHS | Not compliant (per Arrow EU RoHS listing) | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 10KE |
| Logic Elements / Cells | — | 9984 |
| Total RAM Bits | — | 98304 |
| Number of LABs/CLBs | — | 1248 |
| Number of User I/Os | — | 470 |
| Number of Gates | — | 200K system gates |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt) |
| Maximum Operating Frequency | — | 250 MHz |
| Propagation Delay | — | 0.4 ns |
| Package Type | — | 672-ball FBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch |
| Programming Interface | — | JTAG (IEEE 1149.1) + serial/parallel passive configuration |
| Type de montage | — | Surface Mount |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |