EPF10K20RC240-3 vs EPF10K200SRC240-3N Comparaison
Comparaison détaillée côte à côte de EPF10K20RC240-3 par Intel et EPF10K200SRC240-3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K20RC240-3 | EPF10K200SRC240-3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,20 | $162,00 |
| Family | FLEX 10K | FLEX 10KE |
| Series | FLEX-10K® | — |
| Typical Gates | 20,000 | — |
| Logic Elements (LEs) | 12,288 | 9,984 |
| Logic Array Blocks (LABs) | 189 | 1,248 |
| Flip-Flops | 1,152 | — |
| Embedded Array Blocks (EABs) | 6 (2 Kbit each) | 24 |
| Total EAB RAM | 12 Kbits | — |
| User I/Os | 470 (max per package) | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions |
| Boîtier | 240-BFQFP Exposed Pad (RQFP-240) | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch |
| Process Technology | 0.42 µm CMOS, 5 metal layers | 0.22 µm CMOS SRAM |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V tolerant | — |
| Propagation Delay (tpd) | 0.4 ns | — |
| Maximum Internal Frequency | 125 MHz | — |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Speed Grade | -3 | -3 (commercial) |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration PROM | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | unknown (legacy Altera part, likely non-RoHS) | [DATA_NEEDED: RoHS status] |
| Programming | SRAM-based, in-system reconfigurable | — |
| Typical System Gates | — | 200,000 |
| Maximum Logic Elements | — | 9,984 |
| Maximum User RAM Bits | — | 98,304 |
| Propagation Delay (tPD) | — | 0.40 ns |
| Internal Operating Frequency | — | 166.67 MHz |
| Core Supply Voltage | — | 2.5 V |
| MultiVolt I/O Support | — | 2.5 V and 3.3 V interfaces |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) |
| Configuration Method | — | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading |