EPF10K30ATI144-3N vs EPF10K30ATI144-2 Comparaison
Comparaison détaillée côte à côte de EPF10K30ATI144-3N par Altera et EPF10K30ATI144-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPF10K30ATI144-3N - 30K Gate FLEX-10KA FPGA, 102 I/O, TQFP-144
EPF10K30ATI144-3N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPF10K30ATI144-3N | EPF10K30ATI144-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,95 | $21,95 |
| Family | FLEX 10KA | FLEX 10K Embedded Programmable Logic Family |
| Logic Elements / Cells | 1,728 | — |
| Typical Gates | 30,000 | — |
| Logic Array Blocks (LABs) | 216 | — |
| Embedded Memory (EABs) | 12 EABs | — |
| Embedded SRAM | 12,288 bits | — |
| User I/O | 102 | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Maximum Operating Frequency | 125 MHz | — |
| Technology Node | 0.3 µm CMOS | — |
| Boîtier | TQFP-144 (20x20 mm) | 144-pin TQFP (TQFP-144), 0.500 mm pitch |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0°C to +70°C (Commercial) | -40 °C to +85 °C (industrial, 'I' suffix) |
| Speed Grade | -3 (slowest FLEX 10KA bin) | -2 |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Statut RoHS | unknown | Unknown (legacy Altera product line; verify with supplier) |
| Series | — | FLEX 10KA |
| Typical Gate Count | — | 30,000 gates |
| Logic Elements | — | 1,728 cells |
| Embedded Array Blocks (EABs) | — | 12 |
| On-chip RAM | — | 12,288 bits |
| User I/O Pins | — | 246 (max for family), 102 in this 144-TQFP variant per DigiKey listing |
| Propagation Delay | — | 13 ns (per Microchip USA) |
| Process Technology | — | 0.42 µm CMOS, 4 metal layers |
| Core Voltage | — | 5.0 V |
| I/O Voltage Compatibility | — | 5.0 V / 3.3 V / 2.5 V |
| Configuration Method | — | SRAM, in-system programmable |
| JTAG Support | — | IEEE 1149.1 boundary-scan |