EPF10K30EFC256-2X vs EPF10K30EFC256-3N Comparaison
Comparaison détaillée côte à côte de EPF10K30EFC256-2X par Altera et EPF10K30EFC256-3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPF10K30EFC256-2X - 30K FLEX-10KE FPGA 1728 Cells 256-BGA | Intel / Altera
EPF10K30EFC256-2X ObsoleteComparaison des spécifications
| Paramètre | EPF10K30EFC256-2X | EPF10K30EFC256-3N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,95 | $58,00 |
| Series | FLEX-10KE | — |
| Family | FLEX 10KE | FLEX 10KE |
| Gates | 30,000 | — |
| Logic Elements / Cells | 1,728 | 1,728 |
| Number of LABs/CLBs | 216 | — |
| Number of Logic Elements/Cells | 1,728 | — |
| Total RAM Bits | 24,576 | — |
| Number of I/O | 176 | — |
| Voltage - Supply | 2.375 V to 2.625 V | — |
| Température de fonctionnement | 0°C to 70°C | 0 C to +70 C (Commercial) |
| Internal Frequency (Max) | 200 MHz | — |
| Propagation Delay | 0.6 ns | — |
| Technology | 0.22 µm CMOS | — |
| Supplier Device Package | 256-FBGA (17x17) | — |
| Boîtier / Format | 256-BGA | — |
| Type de montage | Surface Mount | — |
| Speed Grade | -2 | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Gate Count | — | 30,000 gates |
| Logic Array Blocks (LABs) | — | 216 |
| Embedded Array Blocks (EABs) | — | 6 |
| Embedded RAM | — | 24,576 bits |
| Maximum User I/Os | — | 176 |
| Boîtier | — | 256-pin FineLine BGA (FBGA) |
| Core Voltage | — | 2.5 V |
| I/O Standard Support | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Frequency | — | 80 MHz (typical) |
| Propagation Delay (tPD) | — | 0.6 ns |
| Bidirectional I/O Performance | — | up to 212 MHz |
| PCI Compliance | — | PCI SIG 2.2 at 33 / 66 MHz |
| Process Technology | — | 0.22 um CMOS |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Open-Drain I/O Option | — | Yes (per pin) |