EPF8282ALC84-4N vs EPF8282ALI84-4 Comparaison
Comparaison détaillée côte à côte de EPF8282ALC84-4N par Altera et EPF8282ALI84-4 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF8282ALC84-4N | EPF8282ALI84-4 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,85 | $8,20 |
| Family | FLEX 8000 | FLEX 8000 |
| Usable Gates | 2,500 | — |
| Logic Elements | 208 | — |
| Maximum User I/Os | 68 | — |
| Package Type | 84-LCC (J-Lead) | — |
| Package Code | QCCJ (Plastic Leaded Chip Carrier, J-Bend) | — |
| Process Technology | 0.42 µm CMOS SRAM | 0.42 µm CMOS SRAM |
| Supply Voltage VCC | 5.0 V | — |
| Output Supply Voltage VCCIO | 3.3 V or 5.0 V (selectable) | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | -40C to +85C (industrial) |
| Configuration Method | Serial (EPC1/EPC1064/EPC1213/EPC1441) or Parallel EPROM or Controller | SRAM (in-circuit reconfigurable) |
| In-Circuit Reconfigurability | Yes (ICR) | — |
| JTAG Boundary-Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Specification compliant | — |
| Dedicated Inputs | 4 (synchronous control signals) | — |
| Type de montage | Surface Mount (J-Lead) | Through-Hole (PLCC socket) |
| Logic Family | CMOS | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Usable Gates (typical) | — | 2,500 |
| Usable Gates (family max) | — | 16,000 |
| Logic Elements / Cells | — | 208 |
| Maximum Operating Frequency | — | 125 MHz |
| Core Supply Voltage | — | 5 V |
| Speed Grade | — | -4 |
| Boîtier | — | 84-pin PLCC |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| Lead-Free / RoHS | — | Non-compliant (legacy PLCC, SnPb finish) |
| Logic Block Architecture | — | Continuous FastTrack interconnect with EABs |