EPF8636ALI84-4 vs EPF8636ALC84-4 Comparaison
Comparaison détaillée côte à côte de EPF8636ALI84-4 par Intel et EPF8636ALC84-4 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF8636ALI84-4 | EPF8636ALC84-4 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,10 | $24,30 |
| Family | FLEX 8000 | FLEX 8000 |
| Usable Gates | 6,000 | — |
| Logic Elements (Cells) | 504 | — |
| Logic Array Blocks (LABs) | 63 | — |
| User I/Os | 68 | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Tension d'alimentation | 5 V | — |
| Process Technology | 0.42 µm CMOS SRAM | 0.42 µm CMOS SRAM |
| Package Type | 84-Pin PLCC (J-Lead) | — |
| Type de montage | Surface Mount | Surface Mount / Socket |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Configuration Method | Serial or Parallel EPROM, JTAG ICR | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| MultiVolt I/O (this package) | No (5 V only for 84-pin PLCC) | — |
| Statut RoHS | [DATA_NEEDED: rohs_status] | Non-compliant (legacy PLCC, lead-bearing) |
| Lead-Free | [DATA_NEEDED: lead_free_status] | — |
| Configuration Devices Supported | EPC1, EPC1064, EPC1213, EPC1441 | — |
| Number of Logic Cells | — | 504 |
| Number of Logic Array Blocks (LABs) | — | 63 |
| Maximum Usable Gates | — | 6,000 |
| Number of User I/O Pins | — | 68 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage (84-pin PLCC) | — | 5.0 V only (3.3 V I/O NOT supported on this package) |
| Operating Current (typical) | — | 10 mA |
| Boîtier | — | 84-Pin PLCC (J-Lead) |
| Speed Grade | — | -4 |
| Configuration Memory Type | — | Volatile SRAM (requires boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |