EPF8820ARC208-24 vs EPF8820ARC208-3 Comparaison
Comparaison détaillée côte à côte de EPF8820ARC208-24 par Altera et EPF8820ARC208-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPF8820ARC208-24 - FLEX 8000 FPGA, 8K Gates, 672 Cells, 208-RQFP | Altera
EPF8820ARC208-24 ObsoleteIntel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoleteComparaison des spécifications
| Paramètre | EPF8820ARC208-24 | EPF8820ARC208-3 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,80 | $62,00 |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Usable Gates | 8,000 | 8,000 |
| Logic Cells | 672 | — |
| Logic Array Blocks (LABs) | 48 | — |
| User I/O Pins | 152 | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Process Technology | 0.42 µm CMOS SRAM | 0.42 µm CMOS |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| I/O Standards | 3.3 V / 5.0 V MultiVolt I/O | — |
| Speed Grade | -24 | — |
| Configuration Method | Serial configuration device (EPC1/EPC1064/EPC1213/EPC1441), parallel EPROM, or JTAG | — |
| In-Circuit Reconfigurability | Yes (ICR) | — |
| Boîtier | 208-pin RQFP (exposed pad) | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial range] | — |
| Statut RoHS | [DATA_NEEDED: not confirmed in datasheet] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED] | — |
| Series | — | FLEX 8000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Configuration Memory | — | SRAM (volatile) |
| Boîtier / Format | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Type de montage | — | Surface Mount |
| Packaging | — | Tray |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |