EPM3032ALC-44-10N vs EPM3032ALC44-7N Comparaison
Comparaison détaillée côte à côte de EPM3032ALC-44-10N par Altera et EPM3032ALC44-7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3032ALC-44-10N - MAX 3000A CPLD, 32MC, 10ns, 44-PLCC | Altera
EPM3032ALC-44-10N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3032ALC-44-10N | EPM3032ALC44-7N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,45 | $1,05 |
| Family | MAX 3000A | — |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 2 | — |
| User I/O Pins | 34 | — |
| Gates | 600 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Speed Grade | -10 (10 ns) | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Logic Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP (IEEE Std. 1532) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Boîtier | 44-pin PLCC | 44-PLCC (J-Lead, 16.59 x 16.59 mm) |
| Température de fonctionnement | 0C to +70C (commercial, -N suffix) | 0C to +70C (commercial grade) |
| Type de montage | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (Intel) |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 32 |
| Logic Gates | — | 600 usable gates |
| Propagation Delay (tPD1) | — | 7.5 ns (max, pin-to-pin) |
| Internal Counter Frequency (fCNT) | — | 227.3 MHz (max) |
| Number of Logic Elements / Blocks | — | 2 LABs (16 macrocells each) |
| Number of I/O Pins | — | 34 usable I/O (44 total package pins) |
| Number of Dedicated Inputs | — | 4 |
| Programmable Type | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Type de mémoire | — | EEPROM (non-volatile, 100 program/erase cycles) |
| Supply Voltage - Internal (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Bank Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Niveau MSL | — | 3 (168 hours) |
| Process Technology | — | CMOS EEPROM |