EPM3128ATC100-7N vs EPM3128ATI100-10 Comparaison
Comparaison détaillée côte à côte de EPM3128ATC100-7N par Intel et EPM3128ATI100-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM3128ATC100-7N - MAX 3000A 128-Macrocell CPLD, 7.5 ns, TQFP-100 | Intel (Altera)
EPM3128ATC100-7N Nrnd
Comparaison des spécifications
| Paramètre | EPM3128ATC100-7N | EPM3128ATI100-10 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3,52 | $8,40 |
| Family | MAX 3000A | MAX 3000A |
| Macro Cells | 128 | 128 |
| Usable Gates | Up to 10,000 | 2,500 |
| Number of I/Os | 80 | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Interface Levels | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | — |
| In-System Programmability | Yes (IEEE 1532 / JTAG) | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| Température de fonctionnement | 0C to +70C (Commercial) | -40 °C to +85 °C (industrial) |
| Boîtier | TQFP-100 (100-pin TQFP, fine-line BGA-256 noted in third-party listings) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| Speed Grade | -7 | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 80 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | — | EEPROM, 3.3 V in-system (JTAG) |
| Process Technology | — | CMOS EEPROM |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |