EPM3256AQC208-10 vs EPM3256AQI208-10 Comparaison
Comparaison détaillée côte à côte de EPM3256AQC208-10 par Altera et EPM3256AQI208-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 ObsoleteAltera
EPM3256AQI208-10 - MAX 3000A 256-Macro CPLD, 10ns, PQFP-208 | Altera
EPM3256AQI208-10 ObsoleteComparaison des spécifications
| Paramètre | EPM3256AQC208-10 | EPM3256AQI208-10 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,20 | $19,95 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | — |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| User I/Os | 161 | 161 |
| Nombre de broches | 208 | — |
| Boîtier | 208-BFQFP (PQFP, Gull Wing) | 208-pin PQFP (Plastic Quad Flat Pack), FQFP code |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Tolerance | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0C to +70C (Industrial suffix 'I' per part number) |
| PCI-SIG Compliance | Yes (speed grades -4, -5, -6, -7, -10) | — |
| Global Clock Networks | 4 (CLK, CLR, OE, GCLK) | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (per lead-free 'Q' suffix) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 95.2 MHz |
| Internal Counter Speed | — | Up to 227.3 MHz |
| Supply Voltage - Core | — | 3.3 V |
| I/O Logic Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, In-System via JTAG (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 |
| Terminal Form | — | Gull-wing SMD |