EPM3256ATC144-10N vs EPM3128ATC144-10N Comparaison
Comparaison détaillée côte à côte de EPM3256ATC144-10N par Altera et EPM3128ATC144-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EPM3256ATC144-10N | EPM3128ATC144-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $14,50 | $6,56 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 128 |
| Usable Gates | 5,000 (up to 10,000 usable in family) | 2,500 (up to 10,000 for full family) |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | 10 ns (speed grade -10) |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Boîtier | 144-LQFP (TQFP, ATC suffix) | 144-pin TQFP |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | 0 °C to +70 °C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 3000A |
| Logic Array Blocks (LABs) | — | 8 |
| User I/Os | — | 96 |
| Counter Frequency (fCNT) | — | 98 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 3.3 V |
| MultiVolt I/O Support | — | 3.3 V / 2.5 V / 1.8 V |
| Configuration Memory | — | EEPROM (in-system programmable, non-volatile) |
| JTAG (IEEE 1149.1) | — | Yes (BST + pin-locking) |
| ISP (IEEE 1532) | — | Yes |