EPM3512AQC208-3 vs EPM3512AQC208-7N Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-3 par Altera et EPM3512AQC208-7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AQC208-3 - MAX 3000A CPLD, 512 Macrocells, 172 I/O, PQFP-208 | Altera
EPM3512AQC208-3 ⚠ Dernier achatAltera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3512AQC208-3 | EPM3512AQC208-7N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,80 | $41,41 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 32 |
| Maximum User I/O Pins | 172 | — |
| Boîtier | PQFP-208 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| Speed Grade | -3 | -7 |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 / JTAG) | — |
| Program/Erase Cycles | 100 minimum [DATA_NEEDED: exact datasheet figure] | — |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial grade range] | 0 °C to +70 °C (commercial) |
| Statut RoHS | [DATA_NEEDED: confirm from datasheet] | Compliant |
| Type de montage | Surface Mount | — |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Logic Capacity | — | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | — | 16 |
| User I/Os | — | 172 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | — | 4 (MultiVolt) |
| Supported I/O Standards | — | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Configuration | — | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1149.1 BST + IEEE 1532 ISP |