EPM3512ATC144-10N vs EPM3256ATC144-10N Comparaison
Comparaison détaillée côte à côte de EPM3512ATC144-10N par Intel et EPM3256ATC144-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM3512ATC144-10N - MAX 3000A CPLD, 512 Macrocells, 144-TQFP | Intel
EPM3512ATC144-10N ✓ ActifAltera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3512ATC144-10N | EPM3256ATC144-10N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,75 | $14,50 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 10000 | 5,000 (up to 10,000 usable in family) |
| Maximum User I/O | 212 | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX in MHz] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | — |
| Boîtier | 144-pin TQFP (TC144) | 144-LQFP (TQFP, ATC suffix) |
| Température de fonctionnement | 0C to +70C (commercial, N suffix) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Statut RoHS | [DATA_NEEDED: RoHS compliance from datasheet] | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Type de montage | Surface Mount | Surface Mount |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | MAX 3000A |
| Macro Cells | — | 256 |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |