EPM5032DC-15 vs EPM5032LC-15 Comparaison
Comparaison détaillée côte à côte de EPM5032DC-15 par Altera et EPM5032LC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete
Comparaison des spécifications
| Paramètre | EPM5032DC-15 | EPM5032LC-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $8,20 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | UV-erasable EPLD (PAL-type CMOS) | — |
| Usable Gates | 600 | 600 |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (4.75 V to 5.25 V) |
| Logic Family | CMOS, TTL-compatible I/O | — |
| Programmable Pins | 16 bidirectional I/O + 4 dedicated input = 20 | — |
| Total Package Pins | 28 | — |
| Boîtier | CERDIP-28 (windowed, through-hole) | JLCC-28 (windowed ceramic) |
| Type de montage | Through-Hole (DIP) | — |
| Température de fonctionnement | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | UV light through ceramic quartz window | — |
| Process Technology | CMOS | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb, ceramic-windowed package) |
| Lead-Free | unknown | — |
| Architecture | — | PAL-type AND/OR with PIA |
| Logic Array Blocks (LABs) | — | 4 |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Technology | — | CMOS EPROM, 1.0 um process |
| Programmability | — | UV-Erasable / OTP |