EPM5032DC-25 vs EPM5032DI-20 Comparaison
Comparaison détaillée côte à côte de EPM5032DC-25 par Altera et EPM5032DI-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5032DC-25 | EPM5032DI-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3,55 | $8,75 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 32 | 32 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: maximum counter frequency] | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Number of Dedicated Inputs | 32 (in DIP-28 pinout) | — |
| Number of I/O Pins | 22 (in DIP-28 pinout, 4 used as dedicated inputs) | — |
| Boîtier | CDIP-28 (Windowed Ceramic DIP-28) | Ceramic DIP-20 (windowed, UV-erasable) |
| Process Technology | CMOS, EPROM (UV-Erasable) | — |
| Architecture | PAL-Type, Single-LAB, 32-Macrocell | CMOS PAL-type EPLD with PIA |
| Output Structure | Programmable I/O with output enable | — |
| Flip-Flop Configuration | D, T, JK, or SR (programmable) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| Statut RoHS | Lead Free / RoHS Compliant (per distributor listings) | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Programming Method | UV erase + Altera/Intel MAX+PLUS II programmer | — |
| Erasure Method | UV light through ceramic window | — |
| Family | — | MAX 5000 (Altera legacy EPLD) |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Product Terms | — | 320 (maximum) |
| Flip-Flops | — | 16 (one per macrocell) |
| Fréquence d'horloge maximale | — | 62.5 MHz |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Programming | — | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |