EPM5032PC-15 vs EPM5032SC-20 Comparaison
Comparaison détaillée côte à côte de EPM5032PC-15 par Altera et EPM5032SC-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5032PC-15 | EPM5032SC-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,10 | $8,75 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable PLD) | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | 32 | — |
| Usable Gates | 600 | — |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | 20 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Boîtier | 28-pin PDIP (PC suffix = windowed CerDIP) | 20-pin SOIC (Small Outline) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | -20 (20 ns) |
| Température de fonctionnement | 0C to +70C (commercial) | 0 °C to +70 °C (commercial grade) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| Statut RoHS | Non-compliant (CerDIP window, contains Be) | [DATA_NEEDED: RoHS status not confirmed in verified data] |
| Lead-Free | No | — |
| Type de montage | Through-Hole (DIP) | Surface Mount |
| Family | — | MAX 5000 |
| Macrocells | — | 32 |
| I/O Pins | — | 16 |
| Outputs | — | 16 |
| Architecture | — | PAL-type, CMOS, UV-erasable |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Tension d'alimentation | — | [DATA_NEEDED: VCC typical range] |
| Technology | — | CMOS EPROM cell |
| Programmability | — | One-time programmable (windowless SOIC) |