EPM5032SC-25 vs EPM5032LC-15 Comparaison
Comparaison détaillée côte à côte de EPM5032SC-25 par Intel et EPM5032LC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5032SC-25 | EPM5032LC-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,20 | $8,20 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable/OTP Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O | 16 | — |
| Total Pin Count | 28 | — |
| Boîtier | PDSO-28 (Plastic DIP Small Outline, SOIC-28 equivalent) | JLCC-28 (windowed ceramic) |
| Speed Grade | -25 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Counter Frequency (fCNT) | 91 MHz | — |
| Supply Voltage (VCC) | 5 V (typical, 4.5 V to 5.5 V) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable or OTP | CMOS EPROM, 1.0 um process |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Type de montage | Surface Mount | — |
| Statut RoHS | [DATA_NEEDED: RoHS status - legacy Altera part; verify with distributor] | Non-compliant (contains Pb, ceramic-windowed package) |
| Programming Method | Altera programming hardware (legacy iMPACT or MAX+PLUS II) | — |
| Architecture | — | PAL-type AND/OR with PIA |
| Usable Gates | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Programmability | — | UV-Erasable / OTP |
| Température de fonctionnement | — | 0C to +70C (commercial) |