EPM5064JC-1 vs EPM5064JC Comparaison
Comparaison détaillée côte à côte de EPM5064JC-1 par Altera et EPM5064JC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5064JC-1 | EPM5064JC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,25 | $7,10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable PLD) |
| Macro Cells | 64 | — |
| Usable Gates | 1250 (typical) | 1,250 (approx.) |
| Logic Elements | 128 (Logic Array Blocks) | — |
| Maximum Operating Frequency | 33.3 MHz (fCNT) | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD typical/max in ns] | [DATA_NEEDED: specific tPD grade value] |
| Supply Voltage (VCC) | 5 V nominal (4.75 V – 5.25 V) | 5 V (typical, 4.75 V - 5.25 V range) |
| Process Technology | 0.8 µm CMOS | — |
| Programmable Pins | 36 (typical I/O, 44-pin PLCC) | — |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | — |
| Boîtier | 44-pin PLCC (J-lead, windowed ceramic) | 68-pin PLCC (JEDEC) |
| Type de montage | Surface Mount (PLCC socket recommended) | Surface Mount (socketed) |
| Température de fonctionnement | 0 °C to +70 °C (commercial, -JC suffix) | [DATA_NEEDED: operating temperature grade] |
| Erasure Method | UV-erasable through quartz window | — |
| Programming Method | Altera Logic Programmer + MasterBlaster/ByteBlasterMV | — |
| JTAG Boundary Scan | Not supported (classic MAX architecture) | — |
| Statut RoHS | Non-compliant (windowed ceramic, contains Pb in glass frit) | [DATA_NEEDED: RoHS compliance] |
| Military/Avionics SMD | 5962-01-417-3750 (QML variant: EPM5064JM/883) | — |
| Macrocells | — | 64 |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |