EPM5064JI-1 vs EPM5064LC Comparaison
Comparaison détaillée côte à côte de EPM5064JI-1 par Intel et EPM5064LC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5064JI-1 | EPM5064LC |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3,40 | $7,10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count from datasheet] | — |
| Boîtier | 68-pin PLCC (windowed ceramic) | PLCC-44 (LCC-44, J-lead) |
| Logic Elements | [DATA_NEEDED: total logic elements] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: combinational tPD from datasheet] | 55 ns |
| Tension d'alimentation | 5 V | — |
| Température de fonctionnement | [DATA_NEEDED: commercial vs industrial grade temp range] | 0C to +70C (Commercial) |
| Process Technology | CMOS, UV-erasable | CMOS EPROM |
| Speed Grade | JI-1 (commercial, -10/-12/-15 family) | — |
| Programmability | UV-erasable (windowed package) | — |
| Data Retention | 25 years (per MAX 5000 datasheet) | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: not stated in provided data] | [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] |
| Programming Type | — | OTP (One-Time-Programmable, UV-erasable EPROM) |
| Macro Cells | — | 64 |
| Usable Gates | — | 1.25K |
| Logic Array Blocks (LABs) | — | 4 |
| Total Inputs | — | 36 (7 dedicated + 29 I/O) |
| I/O Pins | — | 28 bidirectional + 4 dedicated input |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Lead Free | — | [DATA_NEEDED: lead-free status] |