EPM5130WC-2 vs EPM5130LC Comparaison
Comparaison détaillée côte à côte de EPM5130WC-2 par Altera et EPM5130LC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5130WC-2 | EPM5130LC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $62,00 | $15,60 |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable PLD (CPLD) | — |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 45 ns | 55 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.5 V to 5.5 V |
| Température de fonctionnement | 0 °C to 70 °C (Commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Process Technology | CMOS | CMOS (0.7 um EPROM) |
| Dedicated Inputs | 19 | 19 |
| User I/O Lines | 48 | — |
| Total Inputs (I/O + dedicated) | 68 | — |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing | — |
| Terminal Pitch | 0.650 mm | — |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | UV-erasable CMOS EEPROM cells | — |
| Speed Grade | -2 (45 ns) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic JLCC, contains lead) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | AND/OR array with programmable macrocell register | — |
| Series | — | MAX 5000 |
| Family | — | MAX 5000 (EPM51xx) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| User I/O Pins | — | 48 |
| Total Inputs (Dedicated + I/O) | — | 68 |
| Maximum Internal Clock Frequency | — | 50 MHz |
| Global Clock Inputs | — | 1 |
| Configuration Technology | — | UV-Erasable / OTP EPROM |
| I/O Standard | — | TTL-compatible |
| Boîtier | — | JLCC-68 (J-Lead Ceramic Chip Carrier) |