EPM5192AJC-25 vs EPM5192AGC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AJC-25 par Altera et EPM5192AGC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AJC-25 | EPM5192AGC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,20 | $42,00 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | 15 ns |
| Boîtier | PLCC-68 (windowed ceramic, AJC) | 84-pin Ceramic PGA (Pin Grid Array) |
| Nombre de broches | 68 | — |
| Type de montage | Surface Mount | Through-Hole |
| Tension d'alimentation | 5 V (typical) | — |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Température de fonctionnement | [DATA_NEEDED: exact operating temperature range] | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Device Type | — | UV-Erasable/OTP Complex PLD |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Process Technology | — | CMOS |
| Programmable Element | — | UV-Erasable EPROM cell |