EPM5192ALM84-15 vs EPM5192AJC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192ALM84-15 par Altera et EPM5192AJC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteComparaison des spécifications
| Paramètre | EPM5192ALM84-15 | EPM5192AJC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,85 | $18,95 |
| Device Type | OTP Complex Programmable Logic Device (CPLD) | EPLD (Erasable Programmable Logic Device) |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 15 ns (per '-15' speed grade suffix) | — |
| Propagation Delay (vendor-stated) | 25 ns (per MicrochipUSA listing) | — |
| Maximum Internal Frequency | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 5 V (single supply) |
| Technology | CMOS | CMOS, UV-erasable EPROM |
| Programmability | Windowless, OTP (One-Time Programmable) | — |
| Package Type | PLCC-84 (QCCJ, J-bend, square) | — |
| Number of Terminals | 84 | — |
| Terminal Form | J BEND | — |
| Temperature Grade | MILITARY | — |
| Type de montage | Surface Mount / Socket (PLCC) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains Pb, ceramic windowed package) |
| Plage de température de fonctionnement | [DATA_NEEDED: exact military temp range] | — |
| Family | — | MAX 5000 |
| Propagation Delay (tpd) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| Boîtier | — | 84-pin PLCC (J84C) windowed ceramic |
| Température de fonctionnement | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming Method | — | UV-erase + EPROM programming (windowed package) |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Process Technology | — | CMOS EPROM |